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1 features ? ee programmable 524,288 x 1- and 1,048,576 x 1-bit serial memories designed to store configuration programs for field programmable gate arrays (fpgas) in-system programmable via 2-wire bus simple interface to sram fpgas compatible with atmel at6000, at40k and at94k devices, altera flex ? , apex ? devices, lucent orca ? fpgas, xilinx xc3000 ? , xc4000 ? , xc5200 ? , spartan ? , virtex ? fpgas cascadable read back to support additional configurations or higher-density arrays low-power cmos eeprom process programmable reset polarity available in 6 mm x 6 mm x 1 mm 8-lead lap (pin-compatible with 8-lead soic/voic packages), 8-lead pdip and 20-lead plcc packages (pin compatible across product family) emulation of atmel?s at24cxxx serial eeproms available in 3.3v 10% lv and 5v 5% c versions system-friendly ready pin low-power standby mode description the at17c512/010 and at17lv512/010 (high-density at17 series) fpga configuration eeproms (configurators) provide an easy-to-use, cost-effective con- figuration memory for programming field programmable gate arrays. the at17 series is packaged in the 8-lead lap, 8-lead pdip and the popular 20-lead plcc. the at17 series uses a simple serial-access procedure to configure one or more fpga devices. the user can select the polarity of the reset function by programming four eeprom bytes. these devices support a write protection mode and a system-friendly ready pin, which signifies a ?good? power level to the fpga and can be used to ensure reliable system power-up. the at17 series configurators can be programmed with industry-standard program- mers, atmel?s atdh2200e programming kit or atmel?s atdh2225 isp cable. fpga configuration eeprom memory 512-kilobit and 1-megabit at17c512 at17lv512 at17c010 at17lv010 rev. 0944e?12/01
2 at17c512/010/lv512/010 0944e?12/01 pin configurations 8-lead lap 8-lead pdip 20-lead plcc 8 7 6 5 1 2 3 4 data clk reset/oe ce vcc ser_en ceo (a2) gnd 1 2 3 4 8 7 6 5 data clk reset/oe ce vcc ser_en ceo (a2) gnd 4 5 6 7 8 18 17 16 15 14 clk wp1 reset/oe wp2 ce nc ser_en nc ready ceo (a2) 3 2 1 20 19 9 10 11 12 13 nc gnd nc nc nc nc data nc vcc nc
3 at17c512/010/lv512/010 0944e ? 12/01 block diagram device description the control signals for the configuration eeprom (ce , reset/oe and cclk) inter- face directly with the fpga device control signals. all fpga devices can control the entire configuration process and retrieve data from the configuration eeprom without requiring an external intelligent controller. the configuration eeprom reset/oe and ce pins control the tri-state buffer on the data output pin and enable the address counter. when reset/oe is driven high, the configuration eeprom resets its address counter and tri-states its data pin. the ce pin also controls the output of the at17 series configurator. if ce is held high after the reset/oe reset pulse, the counter is disabled and the data output pin is tri-stated. when oe is subsequently driven low, the counter and the data output pin are enabled. when reset/oe is driven high again, the address counter is reset and the data output pin is tri-stated, regardless of the state of ce . when the configurator has driven out all of its data and ceo is driven low, the device tri-states the data pin to avoid contention with other configurators. upon power-up, the address counter is automatically reset. this is the default setting for the device. since almost all fpgas use reset low and oe high, this document will describe reset /oe. eeprom cell matrix row decoder column decoder tc ce clk ready reset/oe ceo(a2) data bit counter osc osc control programming data shift register programming mode logic row address counter power on reset ser_en wp1 wp2
4 at17c512/010/lv512/010 0944e ? 12/01 note: 1. this pin is not available on the 8-lead packages. pin description 8 pdip/ lap pin 20 plcc pin name i/o description 1 2 data i/o three-state data output for configuration. open-collector bi-directional pin for programming. 2 4 clk i clock input. used to increment the internal address and bit counter for reading and programming. 5wp1 (1) i write protect (1). used to protect portions of memory during programming. disabled by default due to internal pull-down resistor. this input pin is not used during fpga loading operations. 36 reset /oe i output enable (active high) and reset (active low) when ser_en is high. a low level on reset /oe resets both the address and bit counters. a high level (with ce low) enables the data output driver. the logic polarity of this input is programmable as either reset/oe or reset /oe. for most applications, reset should be programmed active low. this document describes the pin as reset /oe. 7wp2 (1) i write protect (2). used to protect portions of memory during programming. disabled by default due to internal pull-down resistor. this input pin is not used during fpga loading operations. 48 ce i chip enable input (active low). a low level (with oe high) allows dclk to increment the address counter and enables the data output driver. a high level on ce disables both the address and bit counters and forces the device into a low- power standby mode. note that this pin will not enable/disable the device in the 2- wire serial programming mode ( s er_en low). 5 10 gnd ground pin. a 0.2 ? decoupling capacitor between v cc and gnd is recommended. 614 ceo o chip enable output (active low). this output goes low when the address counter has reached its maximum value. in a daisy chain of at17 series devices, the ceo pin of one device must be connected to the ce input of the next device in the chain. it will stay low as long as ce is low and oe is high. it will then follow ce until oe goes low; thereafter, ceo will stay high until the entire eeprom is read again. a2 i device selection input, a2. this is used to enable (or select) the device during programming (i.e., when ser_en is low). a2 has an internal pulldown resistor. 15 ready (1) o open collector reset state indicator. driven low during power-up reset, released (tri-stated) when power-up is complete. (recommend a 4.7 k ? pull-up on this pin if used). 7 17 ser_en i serial enable must be held high during fpga loading operations. bringing ser_en low enables the 2-wire serial programming mode. for non-isp applications, ser_en should be tied to v cc . 820 v cc +3.3v/+5v power supply pin.
5 at17c512/010/lv512/010 0944e ? 12/01 fpga master serial mode summary the i/o and logic functions of any sram-based fpga are established by a configura- tion program. the program is loaded either automatically upon power-up, or on command, depending on the state of the fpga mode pins. in master mode, the fpga automatically loads the configuration program from an external memory. the at17 serial configuration eeprom has been designed for compatibility with the master serial mode. this document discusses the at40k, at40kal and at94kal applications, as well as xilinx applications. control of configuration most connections between the fpga device and the at17 serial eeprom are simple and self-explanatory: the data output of the at17 series configurator drives din of the fpga devices. the master fpga cclk output drives the clk input of the at17 series configurator. the ceo output of any at17 series configurator drives the ce input of the next configurator in a cascade chain of eeproms. ser_en must be connected to v cc (except during isp). the ready pin is available as an open-collector indicator of the device ? s reset status; it is driven low while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete. cascading serial configuration eeproms for multiple fpgas configured as a daisy-chain, or for fpgas requiring larger configu- ration memories, cascaded configurators provide additional memory. as the last bit from the first configurator is read, the clock signal to the configurator asserts its ceo output low and disables its data line driver. the second configurator recognizes the low level on its ce input and enables its data output. after configuration is complete, the address counters of all cascaded configurators are reset if the reset /oe on each configurator is driven to its active (low) level. if the address counters are not to be reset upon completion, then the reset /oe input can be tied to its inactive (high) level. at17 series reset polarity the at17 series configurator allows the user to program the reset polarity as either reset/oe or reset /oe. this feature is supported by industry-standard programmer algorithms. programming mode the programming mode is entered by bringing ser_en low. in this mode the chip can be programmed by the 2-wire serial bus. the programming is done at v cc supply only. programming super voltages are generated inside the chip. the at17c parts are read/write at 5v nominal. the at17lv parts are read/write at 3.3v nominal. standby mode the at17c/lv512/010 series configurator enters a low-power standby mode when- ever ce is asserted high. in this mode, the configurator consumes less than 0.5 ma of current at 5v. the output remains in a high-impedance state regardless of the state of the oe input.
6 at17c512/010/lv512/010 0944e ? 12/01 example circuits figure 1. at17 series device for programming psli devices notes: 1. reset polarity must be set to active low. 2. use of the optional ready pin is not available on the at17c/lv65/128/256 devices. the fpga con/ done output drives the ce input of the at17 series configurator, while the reset /oe input is driven by the fpga init pin. this connection works under all normal circumstances, even when the user aborts the configuration before con/ done has gone high. a low level on the reset /oe input, during fpga reset, clears the configurator ? s inter- nal address pointer so that the reconfiguration starts at the beginning. figure 2. drop-in replacement of xc17/att17 proms for xilinx/lucent fpga applications notes: 1. reset polarity must be set to active low. 2. use of the optional ready pin is not available on the at17c/lv65/128/256 devices. 3. an internal pull-up resistor is enabled here for done. v cc data0 cclk con init at17 series device ser_en ready (2) data clk ce reset/oe (1) reset at40k/at40kal/at94k gnd reset m2 m1 m0 4.7 k w v cc v cc din cclk done (3) init at17 series device ser_en ready (2) data clk ce reset/oe (1) program xilinx fpga gnd program m2 m1 m0
7 at17c512/010/lv512/010 0944e ? 12/01 for details of isp, please refer to the ? programming specification for atmel's at17 and at17a series fpga configuration eeproms ? , available on the atmel web site, at http://www.atmel.com/atmel/acrobat/doc0437.pdf. figure 3. in-system programming of at17 series for psli applications notes: 1. reset polarity must be set to active low. 2. use of the optional ready pin is not available on the at17c/lv65/128/256 devices. figure 4. in-system programming of at17 series for xilinx/lucent fpga applications notes: 1. reset polarity must be set to active low. 2. use of the optional ready pin is not available on the at17c/lv65/128/256 devices. 3. an internal pull-up resistor is enabled here for done. v 2 4 6 8 10 data 1 sclk 3 5 7 9 ser_en cc v cc v cc 4.7 k w 4.7 k w gnd at17 series device at40k/at40kal/at94k data0 cclk con init ser_en ready (2) data clk ce reset/oe (1) reset gnd reset m2 m1 m0 4.7 k w v cc din cclk done (3) init at17 series device ser_en ready (2) data clk ce reset/oe (1) program xilinx fpga gnd program m2 m1 m0 v 2 4 6 8 10 data 1 sclk 3 5 7 9 ser_en cc v cc v cc 4.7 k w 4.7 k w gnd cc v 4.7 k w
8 at17c512/010/lv512/010 0944e ? 12/01 absolute maximum ratings* operating temperature.................................. -55 c to +125 c *notice: stresses beyond those listed under absolute maximum ratings may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under oper- ating conditions is not implied. exposure to abso- lute maximum rating conditions for extended periods of time may affect device reliability. storage temperature ..................................... -65 c to +150 c voltage on any pin with respect to ground ..............................-0.1v to v cc +0.5v supply voltage (v cc ) .........................................-0.5v to +7.0v maximum soldering temp. (10 sec. @ 1/16 in.).............260 c esd (r zap = 1.5k, c zap = 100 pf)................................. 2000v operating conditions symbol description at17cxxx at17lvxxx units min max min max v cc commercial supply voltage relative to gnd -0 c to +70 c 4.75 5.25 3.0 3.6 v industrial supply voltage relative to gnd -40 c to +85 c 4.5 5.5 3.0 3.6 v military supply voltage relative to gnd -55 c to +125 c 4.5 5.5 3.0 3.6 v
9 at17c512/010/lv512/010 0944e ? 12/01 dc characteristics v cc = 5v ?5% commercial/5v 10% industrial/military symbol description min max units v ih high-level input voltage 2.0 v cc v v il low-level input voltage 0.0 0.8 v v oh high-level output voltage (i oh = -4 ma) commercial 3.86 v v ol low-level output voltage (i ol = +4 ma) 0.32 v v oh high-level output voltage (i oh = -4 ma) industrial 3.76 v v ol low-level output voltage (i ol = +4 ma) 0.37 v v oh high-level output voltage (i oh = -4 ma) military 3.7 v v ol low-level output voltage (i ol = +4 ma) 0.4 v i cca supply current, active mode 10 ma i l input or output leakage current (v in = v cc or gnd) -10 10 a i ccs supply current, standby mode commercial 0.5 ma industrial/military 0.5 ma dc characteristics v cc = 3.3v 10% symbol description min max units v ih high-level input voltage 2.0 v cc v v il low-level input voltage 0.0 0.8 v v oh high-level output voltage (i oh = -2.5 ma) commercial 2.4 v v ol low-level output voltage (i ol = +3 ma) 0.4 v v oh high-level output voltage (i oh = -2 ma) industrial 2.4 v v ol low-level output voltage (i ol = +3 ma) 0.4 v v oh high-level output voltage (i oh = -2 ma) military 2.4 v v ol low-level output voltage (i ol = +2.5 ma) 0.4 v i cca supply current, active mode 5 ma i l input or output leakage current (v in = v cc or gnd) -10 10 a i ccs supply current, standby mode commercial 100 ? industrial/military 100 ?
10 at17c512/010/lv512/010 0944e ? 12/01 ac characteristics ac characteristics when cascading ce reset/oe clk data t sce t lc t hc t cac t oe t ce t oh t hoe t sce t hce t df t oh t cdf t ock last bit t oce t oce t ooe first bit reset/oe ce clk data ceo
11 at17c512/010/lv512/010 0944e ? 12/01 . notes: 1. preliminary specifications for military operating range only. 2. ac test load = 50 pf. 3. float delays are measured with 5 pf ac loads. transition is measured ?200 mv from steady state active levels. notes: 1. preliminary specifications for military operating range only. 2. ac test load = 50 pf. 3. float delays are measured with 5 pf ac loads. transition is measured ?200 mv from steady state active levels. ac characteristics for at17c512/010 v cc = 5v ?5% commercial/v cc = 5v 10% industrial/military symbol description commercial industrial/military (1) units min max min max t oe (2) oe to data delay 30 35 ns t ce (2) ce to data delay 45 45 ns t cac (2) clk to data delay 50 50 ns t oh data hold from ce , oe, or clk 0 0 ns t df (3) ce or oe to data float delay 50 50 ns t lc clk low time 20 20 ns t hc clk high time 20 20 ns t sce ce setup time to clk (to guarantee proper counting) 20 25 ns t hce ce hold time from clk (to guarantee proper counting) 0 0 ns t hoe oe high time (guarantees counter is reset) 20 20 ns f max max input clock frequency 15 15 mhz ac characteristics for at17c512/010 when cascading v cc = 5v 5% commercial/v cc = 5v ?10% industrial/military symbol description commercial industrial/military (1) units min max min max t cdf (3) clk to data float delay 50 50 ns t ock (2) clk to ceo delay 35 40 ns t oce (2) ce to ceo delay 35 35 ns t ooe (2) reset /oe to ceo delay 30 30 ns f max max input clock frequency 12.5 12.5 mhz
12 at17c512/010/lv512/010 0944e ? 12/01 notes: 1. preliminary specifications for military operating range only. 2. ac test load = 50 pf. 3. float delays are measured with 5 pf ac loads. transition is measured ?200 mv from steady state active levels. notes: 1. preliminary specifications for military operating range only. 2. ac test load = 50 pf. 3. float delays are measured with 5 pf ac loads. transition is measured ?200 mv from steady state active levels. ac characteristics for at17lv512/010 v cc = 3.3v 10% symbol description commercial industrial/military (1) units min max min max t oe (2) oe to data delay 50 55 ns t ce (2) ce to data delay 55 60 ns t cac (2) clk to data delay 55 60 ns t oh data hold from ce , oe, or clk 0 0 ns t df (3) ce or oe to data float delay 50 50 ns t lc clk low time 25 25 ns t hc clk high time 25 25 ns t sce ce setup time to clk (to guarantee proper counting) 30 35 ns t hce ce hold time from clk (to guarantee proper counting) 0 0 ns t hoe oe high time (guarantees counter is reset) 25 25 ns f max max input clock frequency 15 10 mhz ac characteristics for at17lv512/010 when cascading v cc = 3.3v 10% symbol description commercial industrial/military (1) units min max min max t cdf (3) clk to data float delay 50 50 ns t ock (2) clk to ceo delay 50 55 ns t oce (2) ce to ceo delay 35 40 ns t ooe (2) reset /oe to ceo delay 35 35 ns f max max input clock frequency 12.5 10 mhz
13 at17c512/010/lv512/010 0944e ? 12/01 thermal resistance coefficients (1) note: 1. for more information refer to the ? thermal characteristics of atmel ? s packages ? , available on the atmel web site, at http://www.atmel.com/atmel/acrobat/doc0636.pdf. package type jc [ c/w] ja [ c/w] airflow = 0 ft/min leadless array package (lap) 8cn4 45 135.71 plastic dual inline package (pdip) 8p3 37 107 plastic leaded chip carrier (plcc) 20j 35 90
14 at17c512/010/lv512/010 0944e ? 12/01 ordering information ? 5v devices memory size ordering code package operation range 512-kbit at17c512-10cc at17c512-10pc at17c512-10jc 8cn4 8p3 20j commercial (0 c to 70 c) at17c512-10ci at17c512-10pi at17c512-10ji 8cn4 8p3 20j industrial (-40 c to 85 c) 1-mbit at17c010-10cc at17c010-10pc at17c010-10jc 8cn4 8p3 20j commercial (0 c to 70 c) AT17C010-10CI at17c010-10pi at17c010-10ji 8cn4 8p3 20j industrial (-40 c to 85 c) ordering information ? 3.3v devices memory size ordering code package operation range 512-kbit at17lv512-10cc at17lv512-10pc at17lv512-10jc 8cn4 8p3 20j commercial (0 c to 70 c) at17lv512-10ci at17lv512-10pi at17lv512-10ji 8cn4 8p3 20j industrial (-40 c to 85 c) 1-mbit at17lv010-10cc at17lv010-10pc at17lv010-10jc 8cn4 8p3 20j commercial (0 c to 70 c) at17lv010-10ci at17lv010-10pi at17lv010-10ji 8cn4 8p3 20j industrial (-40 c to 85 c) package type 8cn4 8-lead, 6 mm x 6 mm x 1 mm, leadless array package (lap) ? pin-compatible with 8-lead soic/void packages 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 20j 20-lead, plastic j-leaded chip carrier (plcc)
15 at17c512/010/lv512/010 0944e ? 12/01 packaging information 8cn4 ? lap 1150 e.cheyenne mtn blvd. colorado springs, co 80906 title drawing no. r rev. 8cn4 , 8-lead (6 x 6 x 1.04 mm body), lead pitch 1.27 mm, leadless array package (lap) a 8cn4 11/14/01 common dimensions (unit of measure = mm) symbol min nom max note a 0.94 1.04 1.14 a1 0.30 0.34 0.38 b 0.45 0.50 0.55 1 d 5.89 5.99 6.09 e 4.89 5.99 6.09 e 1.27 bsc e1 1.10 ref l 0.95 1.00 1.05 1 l1 1.25 1.30 1.35 1 note: 1. metal pad dimensions. pin1 corner marked pin1 indentifier 0.10 mm typ 4 3 2 1 5 6 7 8 top view l b e l1 e1 side view a1 a bottom view e d
16 at17c512/010/lv512/010 0944e ? 12/01 8p3 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8p3 , 8-lead (0.300"/7.62 mm wide) plastic dual inline package (pdip) b 8p3 09/28/01 pin 1 e1 a1 b e b1 c l seating plane a d e eb b2 (4 places) ec common dimensions (unit of measure = mm) symbol min nom max note a ? ? 4.318 a1 0.381 ? ? d 9.144 ? 9.652 note 2 e 7.620 ? 8.255 e1 6.096 ? 6.604 note 2 b 0.406 ? 0.508 b1 1.397 ? 1.651 b2 0.762 ? 1.143 l 3.175 ? 3.429 c 0.203 ? 0.356 eb ? ? 10.922 ec 0.000 ? 1.524 e 2.540 typ notes: 1. this package conforms to jedec reference ms-001 ba. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
17 at17c512/010/lv512/010 0944e ? 12/01 20j ? plcc 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 20j , 20-lead, plastic j-leaded chip carrier (plcc) b 20j 10/04/01 45? max (3x) notes: 1. this package conforms to jedec reference ms-018, variation aa. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. common dimensions (unit of measure = mm) symbol min nom max note a 4.191 4.572 a1 2.286 3.048 a2 0.508 d 9.779 10.033 d1 8.890 9.042 note 2 e 9.779 10.033 e1 8.890 9.042 note 2 d2/e2 7.366 8.382 b 0.660 0.813 b1 0.330 0.533 e 1.270 typ a a1 b1 d2/e2 b e e1 e d1 d
? atmel corporation 2001. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the companys standard warranty which is detailed in atmels terms and conditions located on the companys web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without n otice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of at mel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmels products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 casa postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia atmel asia, ltd. room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan atmel japan k.k. 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory atmel corporate 2325 orchard parkway san jose, ca 95131 tel 1(408) 436-4270 fax 1(408) 436-4314 microcontrollers atmel corporate 2325 orchard parkway san jose, ca 95131 tel 1(408) 436-4270 fax 1(408) 436-4314 atmel nantes la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards atmel rousset zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 atmel colorado springs 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 atmel smart card ics scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive atmel heilbronn theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 atmel colorado springs 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom atmel grenoble avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 atmel configurator hotline (408) 436-4119 atmel configurator e-mail configurator@atmel.com faq available on web site e-mail literature@atmel.com web site http://www.atmel.com printed on recycled paper. 0944e12/01//xm atmel is the registered trademark of atmel. flex is the trademark of altera corporation; orca is the trademark of lucent technologies, inc.; spartan and virtex are the trademarks of xilinx, inc.; apex is the trademark of mips technologies; other terms and product names may be the trademarks of others.

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